European Technology Symposium 2023에서 TSMC측이 확인 해준 내용입니다.

GAA 이후 TR구조 후보로 거론되는 CFET 워킹다이를 연구소 단계에서 확보하였다고 합니다.

- TSMC 자료

- Intel 자료

- IMEC 자료

CFET은 반도체회사 및 연구기관에서 차세대 TR구조로 언급되는 구조로

NMOS와 PMOS를 적층하여 PPA Gain을 얻는 구조로

N/PMOS 얼라인 문제 및 적층 기술 구현 문제 등 많은 어려움이 예상되는 기술입니다.

다만 연구소단계의 성과로 양산 적용까지는 많은 시간이 필요하며 TSMC는 다른 기술 옵션 또한 고려중이기 때문에 가능성 중 하나로 생각하면 좋을 것 같습니다.

관련 발언

"Let me make a clarification on that roadmap, everything beyond the nanosheet is something we will put on our [roadmap] to tell you there is still future out there," said Kevin Zhang, senior vice president at responsible for technology roadmap, business strategy. "We will continue to work on different options. I also have the add on to the one-dimensional material-[based transistors] […], all of those are being researched on being investigated on the future potential candidates right now, we will not tell you exactly the transistor architecture will be beyond the nanosheet."

"Nanosheet is starting at 2nm, it is reasonable to project and that nanosheet will be used for at least a couple of generations, right," asked Zhang rhetorically. "So, if you think about CFETs, we've leveraged [FinFETs] for five generations, which is more than 10 years. Maybe [device structure] is somebody else's problem to worry, then you can continue to write a story."

출처

https://www.anandtech.com/show/18873/tsmc-we-have-working-cfets-in-the-lab-but-they-are-generations-away

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