x86의 ISA가 원체 개판이기 때문에 디코더의 폭을 늘리려고 해도 그것을 위해서는 파이프라인 단수가 추가되어야 하면서 오히려 전반적인 성능에 악영향을 준다는 이야기입니다.

그래서 디코딩폭을 여전히 4way로 억제했다고...

네. 디코딩폭이 좁으면 디코더 뿐만 아니라 전반적인 아키텍처를 넓히는 데 장애물이 됩니다. uOP 캐시가 탱킹한다고 해도 캐시는 어디까지나 캐시죠.  

Being an x86 core, one of the difficulties of the ISA is the fact that instructions are of a variable length with encoding varying from 1 byte to 15 bytes. This has been legacy side-effect of the continuous extensions to the instruction set over the decades, and as modern CPU microarchitectures become wider in their execution throughput, it had become an issue for architects to design efficient wide decoders. For Zen3, AMD opted to remain with a 4-wide design, as going wider would have meant additional pipeline cycles which would have reduced the performance of the whole design.