CPU 코어 구성 내용 중 흥미로운점

L2/L3/시스템 캐시는 이미 공개하였죠?

 

그럼 L1은 어떨까? 궁금한데...

코어별로 살펴 보면

 

- X2

ARM 정보를 보면

instruction Cache 64KB 지원

Data Cache 64KB 지원

 

논문을 보면

The first gear is a single HP core which uses the ARMv9 Cortex-X2 microarchitecture with 64KB L1 instruction cache, 64KB L1 data cache, and a 1MB private L2 cache.

 

-A710

ARM정보를 보면

instruction Cache 32KB/64KB 지원

Data Cache 32KB/64KB 지원

 

논문을 보면

The second gear consists of three Balanced Performance (BP) cores using the ARMv9 Cortex-A710 architecture, each with a 64KB L1 instruction cache, a 64KB L1 data cache, and a 512KB private L2 cache.

 

- A510

ARM 정보를 보면

instruction Cache 32KB-64KB 지원

Data Cache 32KB-64KB 지원

 

논문을 보면

The third gear features four High Efficiency (HE) ARMv9 Cortex-A510 cores, with each core using a 64KB L1 instruction cache, 64KB L1 data cache.

 

네 풀로 다 박아버렸네요.

개인적으로 아쉽다고 느낀점은

A710을 L1까지 풀로 캐시를 박았는데 2.85GHz까지 클럭을 땡겼어야 했나? 싶네요.

조금만 타협했으면 보다 환상적인 전성비를 볼 수 있었을 것 같거든요.

 

그리고 전력 효율을 위한 기술설명도 있던데

요건 관련 이미지와 원문을...

(기술설명을 번역하기는 좀 빡시네요 ㅠ)

To further improve the power efficiency of the CPU subsystem, the design uses an adaptive voltage scaling (AVS) architecture by combining frequency-locked loop (FLL) and variation-resistant CPU speed binning technologies.

The FLL architecture addresses the challenge of limited power supply bandwidth, but is unable to cover for long-term (>ms) DC variations, such as supply load regulation or temperature variations. To achieve full-bandwidth protection and voltage margin reduction, a digitally controlled Ring Oscillator (ROSC) frequency-limiting mechanism is added to the FLL, to provide an operating condition reference. This is achieved by applying a minimum fine code (minFC) that the ROSC is allowed to operate on.

When the operating condition degrades, such as increased IR-drop, the FLL clock frequency will be limited to guarantee safe CPU operation. A voltage increase request, sent to the PMIC, is generated by comparing the FLL output frequency to the PLL input frequency. Conversely, when operating conditions improve and extra voltage margin is no longer needed, the ROSC will oscillate at PLL frequency with a fine code higher than minFC. A voltage decrease request will be sent to the PMIC to reduce the supply voltage until the FLL is frequency locked while using minFC for the ROSC.

 

마지막으로

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